Basic Combinational Logic Elements (Ch. 6) Notes Outline

ENGR-171
Winter 2024
\[\gdef\W{\Omega} \gdef\w{\omega} \gdef\u{\mu} \gdef\a{\alpha} \gdef\I{\hat{I}} \gdef\V{\hat{V}} \gdef\H{\hat{H}} \gdef\S{\hat{S}} \gdef\z{\mathbf{z}} \gdef\Z{\mathbf{Z}} \gdef\Vrms{\ V_{rms}} \gdef\Arms{\ A_{rms}} \gdef\deg{^\circ} \gdef\e#1{\times 10^{#1}}\]

In chapter 6 we start looking at logic circuits that do a function. To this point we have just looked at gates and describing logic with equations. Now we are going to look at some system level functions. We will talk about logic as a system function not just as a bunch of gates.

The complex functions we are building in Chapter 6 are just the beginning. We will use basic gates to build these functions. Later we will use these functions to build bigger more complex functions. That is how the hierarchy of digital logic works. We start building small functions (gates) and use those to build bigger functions, and then bigger functions. It means we don’t have to design every part from scratch.

In your journey you are just starting with digital logic. So we started with the smallest functions, gates. Now we are ready to make the next step.

We are skipping sections 6.1 and 6.2 of this chapter. In 271 we will talk more about memories used as memories. 6.1 explains how we can use memory chips to perform complex functions. We will talk about this some also in 271 when we talk about FPGAs.

For now, lets focus on functions we can realize with our basic gates: decoding / selecting and Multiplexing. These functions are some of the most common we will see in the digital world.

6.3 Decoding and Selecting

Decoding and Selecting are generally used together. Usually what happens is there is a binary number that represents a particular logic gate. We decode this number and use that information to select the correct gate. This idea is used in all computer systems. It is the fundamental principal on how different blocks of memory are selected. It is what allows us to expand memory in our computers by adding another RAM DIMM (card). Figure 6-12 and 6-13 show some high level examples of this.

Figure 6-12.
  • You start with a 2-bit binary number (0-3).
  • 2-4 decoder: 2 inputs, 4 outputs (Y3,Y2,Y1,Y0). The binary number on the input, represents which output line is active.
    • Y0 is active if the input number = 0
    • Y1 is active if the input number = 1 and so on
    • Input: 11, output: 1000; Input 01, output: 0010; Input: 00, output 0001
  • Enable bits and address bits: These terms directly apply to memory systems. But they also apply to other systems.
    • Enable bits are a signal on a chip that turns the chip on. If a chip is not enabled, it doesn’t produce output and ignores all other inputs.
    • Address bits are the binary number that is input to the decoder. It is the address of the chip you want to enable.
    • The output of the decoder goes to the different chips as the enable.

One reason to do this is transportation of information. I’m going to stay with the Computer example. The computer wants data from a specific spot 2 in memory. It then sends a binary 2 (2 digits) to the memory board and the memory board decodes this information to figure out what chip to enable. The alternative is the CPU has to decode the information and send an enable signal to each memory chip on the memory board. For a 2-4 decoder this doesn’t seem like a big waste. But think about if you had 8 chips. That is 8 lines, or you can encode the information into a binary number and then you just need 3 lines for the correct address.

6.3.2 Binary Decoders

  • The most common decoders. They decode a binary input number to an output. What I described in the previous section is a binary decoder
  • Many decoders have an Enable signal as well. This is not a requirement, just something that happens.
  • Table 6-3 and Figure 6-15 show the truth table and circuit design for a 2-4 decoder with an enable.
‼ Important

The X in the first row of table 6-3 for A1 and A0 represents a DON’T CARE state. This means that it doesn’t matter if A1 is a 1 or 0. The output result is the same.

  • Table 6-3 uses the X states to shorten the truth table. When EN=0, the outputs aren’t controlled by A1 and A0. So A1 and A0 don’t matter. This means we don’t have to list all combinations. We can list A1 and A0 as X.
    • EN=1 now the decoder works and the Y outputs are set based on the address input (A1, A0).
  • Notice how the Enable is built in Figure 6-15. If it is one than those AND gates do something, if it is 0, then the AND gates are off.
  • Table 6-4 shows the truth table for a 3-8 decoder with 3 input enables
    • I don’t know why there are 3, but for some reason that is pretty common.
      • I think mostly for expandability, but I don’t know a specific example.
      • The enables are labeled with G. G stands for Gate as in this signal can gate off the output
      • G1 is active High
      • G2A_L and G2B_L are both active Low
    • Outputs are active Low
    • I don’t like the way they did the address bits. C=MSB and A=LSB. This is not clear. I would prefer A2, A1, A0. Where A2=MSB
      • Sometimes you have to interpret the data sheet
‼ Important

Look up the 74x138 data sheet and find the truth table for the logic. Does this make sense to you. Also notice that the Enables are organized differently than in the truth table shown in Table 6-4.

  • Figure 6-17 shows how the 74x138 might be built. Notice this is just a bigger version of figure 6-15.
  • Figure 6-16 shows the schematic symbol used for the 74x138.
    • This generic box doesn’t give you any indication of the functionality of the circuit. It tells you inputs and outputs. To know what it does you have to look up the part number and find the truth table for that chip
    • Some schematic symbols do indicate functionality. Logic symbols used to indicate functionality, generally don’t show pinouts. This means they don’t tell you how to build the circuit, just what the circuit function should do logically.

6.3.3 Larger Decoders

Here we have an answer as to why so many enable pins. In Figure 6-19 we use 5 74x138 chips to build a 5-32 decoder. 4 of the chips decode the 32 outputs. All of these decoders are using the same 3 input addresses (N2, N1, N0). If N2,N1,N0 is 000 all 4 of the output chips want to turn on their Y0 output. But only one of these 4 decoders is enabled. The 5th decoder decodes the address from N4, N3 to decide which decoder to enable. If N4, N3=00 then we know that the input is one of the first 8 lines and Decoder 0 should be enabled. If N4, N3=10 then the input address is between 16-23 and that is decoder 2.

  • This configuration is called cascading We have added a decoder (N4,N3) in series with the other decoders. If the address changes then that information must pass through the N4/N3 decoder and then an output decoder.
    • As designs get bigger this cascading delay can add up and really slow down the system.

Cascading is a series approach (in a line). The alternative approach is to do more things in parallel. Parallel logic means that multiple pieces of information are decoded a the same time. Parallel implementation is usually faster but also larger than series implementation. There is always a trade-off between speed and size

  • Parallel implementation is sometimes called predecoding. Predeocoding is decoding some of the information before you do the main decoding.
  • Figure 6-20 shows how predecoding is used to make a 6-64 decoder.
    • Each pair of address is decoded into 4 outputs. This converts our 6 bit input to a 12 bit intermediate output.
    • The intermediate outputs are then combined at the output stage to produce the final output.
    • Y0=EN · A5' · A4' · A3' · A2' · A1' · A0'
    • Y63 = EN · A5 · A4 · A3 · A2 &middot A1 · A0

6.3.4 Decoders in Verilog

READ this section for information. We will not be doing Verilog this term * Verilog is a HDL (Hardware Description Language). It is coding for digital logic. * Computers have gotten really good at putting gates and logic functions together so we generally let them. Most large digital designs are described in Verilog and then the computer creates the logic. * We do not do Verilog in 171. We will do Verilog in 271.

6.3.5 Custom Decoders

READ for information

6.3.6 Seven-Segment Decoders

These decoders are extremely common. They are still used even with LCD displays (I think). * Figure 6-23 shows how 7 LED (light) segments can be configured to produce the numbers 0-9. 7 segment Displays can actually do 0-F. We have 7 segment displays in the lab

This section mostly talks about how to build a BCD - 7 Segment decoder in Verilog. The goal of this section is to introduce you to the 7-segment display. This is the most common display you will use in school for producing numbers and letters. Decoding binary to properly work this display is important.

The 74x4511 is a BCD-7 segment decoder chip that we have in the lab. You should look up the data sheet for this chip and see how it works.

6.3.7 Encoders

Encoders are the dual function of decoders. Encoders have an input for each signal and then they encode that information into a binary number. This is useful in a system that might have lots of binary sensors. The data from 8 binary sensors could be encoded into a 3-bit number and sent to a controller to determine what to do next. This makes the wiring simpler between the sensor block and the controller block.

  • The encoders in Figure 6-24 are priority encoders. They assume only 1 input is active at a time. There are 8 inputs. Only 1 is active. The output address is the line number of the active input signal.
    • Notice that line I0 basically isn’t used. If I0=1 then Y2,Y1,Y0 should all be 0. So that works out.

6.4 Multiplexing

Decoding was about taking an input and enabling different outputs. Multiplexing is about switching. A multiplexer takes an input, decodes that input and then uses the decoded value to select data to connect to the output. * Inputs: Select signals, data inputs * Outputs: 1 output

Multiplexers (MUX) are electronically controlled multi-position switches. Figure 6-25 shows a switch being used as a MUX. Figure 6-26 shows how a decoder is used as part of a MUX. The decoder decodes the input address to enable one of the switches. We don’t usually build MUXs with this way. Usually we incorporate the decoding and selecting into one gate, see Figure 6-29

  • Example:
    • 2 data inputs (D1, D0), this requires a 1 bit select (SEL)
    • 1 data output (Y).
    • If SEL=0 then Y=D1. Y=1 if D1 is 1 and Y=0 if D1=0. If D1 changes, Y will change.
    • If SEL=1 then Y=D0. Y=1 if D0 is 1 and Y=0 if D0=1. If D0 changes, Y will change.
    • The SEL input controls which data signal (D1, or D0) will be connected to the output.

Figure 6-27 shows how we use CMOS transistors to build a MUX function or chip. This is how the transistors are configured. We are not focusing on transistors in this class, so just enjoy the beauty of drawing, but don’t worry too much about the hows.

6.4.1 Gate-Level Multiplexer Circuits

Figure 6-28 and Figure 6-29 show how we use gates as switches. These two figures perform mostly the same function. 6-28 is a generic MUX circuit that uses a decoder block. 6-29 is a specific 4 input MUX. This circuit has combined the decoding and selecting into one AND gate.

  • Figure 6-28
    • The top AND gate combines D0 and Y0. If S=0, then Y0 will be a 1 and this AND gate will be the only AND gate active (enabled, or turned on). The output of this AND gate depends on D0. The output of this AND gate will be whatever D0 is: D0=1, AND=1. Going into the OR gate all inputs are a 0, except for the input from the top AND gate. That signal can be a 1 or 0. So the output will be whatever D0 is. If D1 is a 1, that doesn’t matter because Y1=0 and the AND gate that combines Y1 and D1 will output a 0.
  • Figure 6-29
    • The function is the same as 6-28 except that the decoder is integrated into the switch.
    • Recall from Figure 6-15 that the decoder is basically an AND gate.
    • Now we add to the decoder AND gate the data input (D) that corresponds to the appropriate selection.
      • D0 connects to the AND gate that is connected to S0' and S1'. If S1,S0=00 then the output of the top AND gate will be the value of D0. All other AND gates will output a 0. The Y output will only be a 1 if D0=1 in this case.
  • Figure 6-30
    • This is a 8 input, 1-bit MUX. Their are 8 different input signals, each is only 1 bit.
    • The 1-bit part is important because it is possible to MUX a data bus. See Figure 6-31
    • Read the Blue box about Extra Inverters These inverters don’t perform a logic function. They are needed to real world circuit applications as a buffer to help timing.
  • Figure 6-31
    • This is a multi-bit MUX. Each data input is a bus (multiple signals). When D0 is selected, D0[0] is connected to Y[0], D0[1] is connected to Y[1]
    • D0[0] is the LSB of the D0 bus
    • D1[1] is the 2nd bit of the D1 bus
    • In this circuit Y is a multi bit signal. Each Y output is controlled by a bit of the selected data bus
  • Figure 6-32 / Table 6-7
    • This circuit is a realization of the generic figure 6-31
    • There are 2 inputs (D0 and D1). Each input is 4 bits wide (1D0, 2D0, 3D0, 4D0)
      • I don’t like this numbering. Normally the LSB is bit 0, not bit 1.
    • There are 4 outputs (1Y, 2Y, 3Y, 4Y)
    • Output 1Y is either 1D0 or 1D1. It is the value of 1D0 if S=0 and 1D1 if S=1
    • Look closely at the schematic
      • The top NOR gates are a decoder
      • The data bits are in slices. The same circuit is repeated 4 times. The two AND gates and OR gate are a 1-bit MUX. This circuit is repeated 4 times, once for each data bit
      • As circuits get bigger and more complex, the idea of having slices and pieces of identical circuits is beneficial. If the 1 bit MUX works, then you know that is a safe circuit block to use for that function again. If 2Y is not working properly, it is a connection issue, not a logic issue
  • Figure 6-33
    • We don’t always want to build a large MUX with basic gates. 6-33 shows how we can use 8 input, 1-bit MUX blocks to build a 32-input MUX.
    • We need 4 8-bit MUX blocks
    • Each 8 bit MUX will have the same select bits for inputs. (XS2, XS1, XS0). That leaves 2 select bits not used yet (XS4, XS3).
    • A decoder is used with the XS4 and XS3. This decoder decides which slice (MUX) should be enabled. If XS4=0 and XS3=0, then ENABLE XO0 MUX. If XS4=1 and XS3=0, enable XO2 MUX
    • This is similar to the way we expanded our decoder in Figure 6-19

6.4.3 Multiplexers, Demultiplexers, and Busses

  • A Demultiplexer (DMUX) is the dual circuit of a MUX. It takes 1 input and sends it to 1 of n possible outputs
    • This is similar to the relationship between an DECODER and ENCODER
  • DMUX can be built using an ENCODER: Figure 6-35
    • In this example the data to be sent out is connected to the EN bit.
      • If data is a 0, then the chip is disabled and all outputs are 0
      • If data = 1, chip is enabled and only the selected output is set to 1. All other outputs are 0.
  • Read the blue box about WORTHLESS
    • The comment of the author makes of just sending all the data and letting the destination sort it out. Destinations that don’t need the data would not be ENABLED, thus they would ignore the data. It is likely the destination already has an enable signal so this makes sense as a way to simplify the overall circuit
    • I personally don’t think you will commonly encounter a DMUX. I think they are interesting here as a dual concept to the MUX. The idea of duality is important in Electrical Engineering. It helps us simplify some complex ideas
‼ Important

The symbols in Figure 6-34 are common MUX and DEMUX logic symbols. These symbols represent the MUX functionality. They don’t show pins. If you see a trapezoid symbol like this, assume it is a MUX (or DMUX, depending on data direction). Input is on the left.

6.4.4 Multiplexers in Verilog

Read for information We will explore Verilog in 271